datasheet low phase noise zero dela y buffer and multiplier ICS670-01 idt? low phase noise zero delay buffer and multiplier 1 ICS670-01 rev l 012315 description the ICS670-01 is a high-speed, low phase noise, zero delay buffer (zdb) which integrates idt?s proprietary analog/digital phase locked loop (pll) techniques. the zero delay feature means that the rising edge of the input clock aligns with the rising edges of the outputs. there are two identical outputs on the chip. fbclk should be connected to fbin. each output has its own output enable pin. the ICS670-01 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to video. by allowing off-chip feedback paths, the ICS670-01 can eliminate the delay through other devices. the 15 different on-chip multipliers work in a variety of applications. arbitrary multiplication factors (including fractions) can be configured on the ics527. features ? packaged in 16-pin soic ? pb (lead) free package, rohs compliant ? clock inputs from 5 to 160 mhz (see page 2) ? patented pll with low phase noise ? output clocks up to 160 mhz at 3.3 v ? 15 selectable on-chip multipliers ? power down mode available ? low phase noise: -124 dbc/hz at 10 khz ? output enable function tri-states outputs ? low jitter?15 ps one sigma ? full swing cmos outputs with 25 ma drive capability at ttl levels ? advanced, low power, sub-micron cmos process ? industrial temperature version available ? operating voltage of 3.3 v or 5 v block diagram voltage controlled oscillator fbclk oe1 phase detector, charge pump, and loop filter fbin s3:s0 iclk clk2 4 oe2 vdd 3 gnd 3 external feedback from fbclk is recommended. rom- based multipliers
ICS670-01 low phase noise zero delay buffer and multiplier zdb and multiplier idt? low phase noise zero delay buffer and multiplier 2 ICS670-01 rev l 012315 pin assignment multiplier select table pin descriptions 12 1 11 2 10 3 9 vdd 4 vdd 5 vdd 6 gnd 7 clk2 8 oe2 gnd s0 s1 fbclk s3 oe1 iclk 16 15 14 13 fbin gnd s2 s3 s2 s1 s0 clk2 (and fbclk) input range (mhz) 0000low (power down entire chip) - 0001 i nput x1.333 18 - 120 0010 input x6 5 - 26.67 0011 i nput x1.5 16.67 - 107 0100 i nput x3.333 7.5 - 48 0101 i nput x2.50 10 - 64 0110 input x4 6 - 40 0111 input x1 25 - 160 1000 i nput x2.333 11 - 69 1001 i nput x2.666 10 - 60 1010 input x12 5 - 13.33 1011 input x3 8 - 53.33 1100 input x10 5 - 16 1101 input x5 6 - 32 1110 input x8 5 - 20 1111 input x2 12 - 80 pin number pin name pin type pin description 1 - 3 vdd input power supply. connect all pins to the same voltage (either 3.3 v or 5 v). pins 1 and 2 supply the analog sections of the chip. 4 clk2 output clock output from vco. output frequency equals the input frequency times multiplier. 5 oe2 input output clock enable 2. tri-states the clock 2 output when low. 6 fbclk output clock output from vco. output frequency equals the input frequency times multiplier. 7 oe1 input output clock enable 1. tri-states the feedback clock output when low. 8 fbin input feedback clock input. 9 iclk input clock input. connect to a 5 - 210 mhz clock. 10 s3 input multiplier select pin 3. determines outputs per table above. internal pull-up. 11 s2 input multiplier select pin 2. determines outputs per table above. internal pull-up. 12 s1 input multiplier select pin 1. determines outputs per table above. internal pull-up. 13 s0 input multiplier select pin 0. determines outputs per table above. internal pull-up. 14 - 16 gnd power connect to ground.
ICS670-01 low phase noise zero delay buffer and multiplier zdb and multiplier idt? low phase noise zero delay buffer and multiplier 3 ICS670-01 rev l 012315 external components the ICS670-01 requires a minimum number of external components for proper operation. decoupling capacitors of 0.01f should be connected from each vdd pin to the ground plane, as close to the device as possible. a series termination resistor of 33 ? should be used to each clock output pin. absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ICS670-01. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics vdd=3.3v 10%, ambient temperature -40 to +85 ? c, unless stated otherwise item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature 0 to +70 ? c ambient operating temperature, ICS670-01i -40 to +85 ? c storage temperature -65 to +150 ? c junction temperature 125 ? c soldering temperature 260 ? c parameter min. typ. max. units ambient operating temperature 0 +70 ? c power supply voltage (measured in respect to gnd) +3.0 +5.5 v parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 5.5 v input high voltage v ih 2v input low voltage v il 0.8 v output high voltage v oh i oh = -12 ma 2.4 v output low voltage v ol i ol = 12 ma 0.4 v output high voltage, cmos level v oh i oh = -4 ma vdd-0.4 v operating supply current idd no load 35 ma short circuit current i os each output 50 ma internal pull-up resistor r pu oe, select pins 200 k ? input capacitance c in oe, select pins 5 pf
ICS670-01 low phase noise zero delay buffer and multiplier zdb and multiplier idt? low phase noise zero delay buffer and multiplier 4 ICS670-01 rev l 012315 ac electrical characteristics vdd = 3.3v 10%, ambient temperature -40 to +85 ? c, unless stated otherwise note 1: rising edge of iclk compared with rising edge of clk2, with fbclk connected to fbin, and 15 pf load on clk2. see graph on page 5 for skew vs. frequency and loading. thermal characteristics parameter symbol conditions min. typ. max. units input clock frequency f in see table on page 2 5 160 mhz output clock frequency 160 mhz pll stabilization time t stab input frequency 5 mhz to 160 mhz 4 10 s output rise time t or 0.8 to 2.0 v, no load 1.5 ns output fall time t of 2.0 to 0.8 v, no load 1.5 ns output clock duty cycle t dc measured at vdd/2 45 50 55 % input to output skew note 1 100 ps maximum absolute jitter short term 45 ps maximum jitter one sigma 15 ps phase noise, relative to carrier, 125 mhz (x5) 100 hz offset -110 dbc/hz 1 khz offset -122 dbc/hz 10 khz -124 dbc/hz 200 khz -117 dbc/hz parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 120 ? c/w ? ja 1 m/s air flow 115 ? c/w ? ja 3 m/s air flow 105 ? c/w thermal resistance junction to case ? jc 58 ? c/w
ICS670-01 low phase noise zero delay buffer and multiplier zdb and multiplier idt? low phase noise zero delay buffer and multiplier 5 ICS670-01 rev l 012315 figure 1. skew fr om iclk to clk2 , with change in load capacitance (vdd = 3.3v) adjusting input/output skew the data in figure 1 can be used to adjust individual ci rcuit characteristics and achieve the minimum possible skew between iclk and clk2. with a 125 mhz output, for example, having a total lo ad capacitance of 15 pf will result in nearly zero skew between iclk and clk2. note that the load capacitance includes board trace capacitance, input capaci tance of the load being driven by the ICS670-01, and any additional capacitors connected to clk2. figure 2. phase noise for 125 mhz output, 25 mhz clock input (vdd = 3.3v) -400 -300 -200 -100 0 100 200 300 25 50 75 100 125 150 clk2 frequency (mhz) skew (ps) skew (ps) 20 pf skew (ps) 10 pf ics670 phase noise -140 -120 -100 -80 -60 -40 -20 0 10.e+0 100.e+0 1.e+3 10.e+3 100.e+3 1.e+6 10.e+6 offset frequency l(f) dbc
ICS670-01 low phase noise zero delay buffer and multiplier zdb and multiplier idt? low phase noise zero delay buffer and multiplier 6 ICS670-01 rev l 012315 package outline and package dimensions (16-pin soic, 150 mil. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information "lf" suffix to the part number denotes pb-free configuration, rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integr ated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for us e in normal commercial applications. any ot her applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommen ded without additional pr ocessing by idt. i dt reserves the right to change any circuitry or specificat ions without notice. idt does not authorize or warrant any idt product for use in life suppor t devices or critical medical instruments. revision history part / order number marking shipping packaging package temperature 670m-01lf 670m-01lf tubes 16-pin soic 0 to +70 ? c 670m-01lft 670m-01lf tape and reel 16-pin soic 0 to +70 ? c 670m-01ilf 670m-01ilf tubes 16-pin soic -40 to +85 ? c 670m-01ilft 670m-01ilf tape and reel 16-pin soic -40 to +85 ? c index area 1 2 16 d e seating plane a1 a e - c - b .10 (.004) c ? c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 9.80 10.00 .3859 .3937 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 ? 0 ? 8 ? 0 ? 8 ? rev. date originator description of change l 01/23/15 rdw updated ac characterization table with new parameter "pll stabilization time".
? 2015 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/clockhelp innovate with idt and accelerate your future netw orks. contact: www.idt.com ICS670-01 low phase noise zero delay buffer and multiplier zdb and multiplier
|
